Silicon integrated circuits have been progressed in enlarging the scale as well as in improving the performance according to so-called Moore's rule, and supported the development of the advanced information technology (IT) society from an aspect of the hardware. This trend is expected to be continued also in future. However, it is deeply concerned that miniaturization of the conventional bulk type CMOS integrated circuit will reach its limit in near future. Its main reasons are an increase in leakage current due to the miniaturization of the transistor, a degradation in switching property of the transistor (an increase in the sub-threshold slope) and so on. In other word, a serious problem lies in that the more the technology node progresses, the more percentage of inefficient power consumption due to the leakage current rather than the operating power increases.
In order to overcome this essential difficulty, the ITRS road map has declared an introduction of an ultra-thin body, fully depleted SOI (Silicon-On-Insulator) device, double-gate/multi-gate MOSFET and so on in an early stage of the decade from 2010 year. Especially, a global attention has been directed towards a fin type double gate MOSFET (FinFET) having a standing, lateral channel (Refer to Non Patent Document 1) as a promising candidate device after the 32 nm node. Even with this double gate MOSFET, however, it is still not easy to perfectly suppress increase of the leakage current and the sub-threshold slope due to the short channel effect when the gate length of the device is decreased to 20 nm or below (corresponding to a stage after the 32 nm node). Furthermore, the dimension of the channel is required to be small corresponding to shortening the gate length, but forming the small channel is difficult.
Since the threshold voltage of the FinFET described above is a fixed value, it is not available for applications such as dynamic electric power control. Proposal to overcome such a drawback has already been made. For example, Patent Document 1 and 2 realizes threshold voltage control by physically separating and electrically isolating the gate electrodes which sandwich a vertical type channel, by applying a fix bias voltage to one of the gate electrodes, and by driving the transistor with the other gate electrode. By changing the fixed bias voltage value, the drain current versus gate voltage characteristics (Id-Vg) of the transistor shifts horizontally, thereby enabling the threshold voltage control.
When the threshold voltage is controlled by a gate voltage on one side, however, the sub-threshold slope inevitably increases significantly from the ideal value S=60 mV/decade, which leads to a degradation of the switching characteristics of the device. Further problem is that the drain current decreases significantly when the threshold voltage is controlled by applying a voltage to one of the gate electrodes, since the gate bias works to a direction for one of the channels to close.
In recent years, a silicon nano-wire field effect transistor has been actively studied and developed as a device structure to break through the limit of the channel miniaturization in order to overcome the problems such as the short channel effect, decrease in the driving current, difficulty in formation of a fine channel and so on described above for the FinFET. A silicon nano-wire field effect transistor such as shown, for example, in FIGS. 29, 30 and 31 has been proposed (Non Patent Document 2 and 3). Features of such a device structure include the channel having a nano-meter sized circular cross-section shape, and a gate electrode covering around the channel. This structure has, therefore, a stronger controllability to a channel potential by the gate and is more effective in suppressing the short channel effect compared with the FinFET. This structure also gives some latitude in channel miniaturization. In other words, the dimension of the channel can favorably be larger than the gate length. This is resulted from that the gate electrode tightly covers all around the channel (Gate-All-Around: GAA) in the nano-wire field effect transistor, whereas the gate electrode covers only two sides of the channel in FinFET.
In order to increase the driving current, a plurality of nano-wires each having a circular cross-section shape are arranged laterally in the nano-wire field effect transistor proposed so far, as shown, for example, in FIGS. 32, 33 and 34. This structure, however, would enlarge the device area.    Patent Document 1: Japanese Patent Application Publication No. 2002-270850.    Patent Document 2: Japanese Patent Application Publication No. 2005-167163.    Non Patent Document 1: IEEE Trans. Electron Devices, Vol. 47. No. 12, pp. 2320-2325, 2000.    Non Patent Document 2: Symposium on VLSI Technology 2004, pp. 196-197.    Non Patent Document 3: Sung Dae Suk, et al., IEDM Tech. Dig., pp. 735-738, 2005.